6502 processor basics
Depending on how you look at it, the 6502 can be considered as having
1, 3, or 6 registers.
In one point of view, the A register is the only real general purpose
register, and all the others are unique and special.
The point of view that I think is most accurate, is to say that it has
three registers: A, X, and Y. The PC, P, and S registers are so special
purpose they don't really deserve to be called registers at all.
Registers:
- A - 8 bit accumulator
- X - 8 bit index register
- Y - 8 bit index register
- PC - 16 bit program counter (PCH/PCL)
- S - 8 bit stack pointer
- P - 8 bit condition code (status register)
bits in the status register:
- N - negative
- V - overflow
- 1 - always one
- B - BRK command
- D - decimal mode
- I - IRQB disabled if set
- Z - zero
- C - carry
Addressing modes
Pay attention!
If you get all this straight, you know most of what you need
to know to understand this chip.
There is some weird stuff here.
Byte 1 is the opcode for the instruction being executed.
Some instructions have additional information in one or two bytes that follow.
- Implied - a single byte instruction involving only registers
or some explicit processor action. Examples: CLI, TAY, PHA
- Accumulator - a single byte instruction that explicitly targets the
accumulator. Examples: DEC A, ASL A, LSR A, ROL A, ROR A
These are all instructions that could reference memory via some other addressing
mode, but can reference the accumulator if it is explicitly specified.
- Absolute - bytes 2 and 3 give the 16 bit address. Examples: STA $A010, JSR $C00F
- Immediate - byte 2 is the operand. Example: LDA #$ff
No memory is accessed (other than instruction fetch), the value is part of the instruction.
- PC relative - add byte 2 to PC and go there. Used only by branch instructions. Example: BNE $CA0D
- Zero page - byte 2 addresses 00xx. Example: ADC $18
- Absolute indexed with X (or Y) - add X (or Y) index register to bytes 2 and 3 to give address.
Note that fewer instructions can use Y indexing than can use X indexing.
Example: LDA $A513,X
- Zero page, indexed by X (or Y) - byte 2 plus X (or Y) yields effective address.
Fewer instructions (only LDX and STX) can use Y indexing than can use X indexing.
Example: STA $B3,X
This implies a table of bytes in the zero page.
- Indirect absolute
The instruction provides a two byte address from which a two byte address is
fetched and jumped to.
Used only by JMP, Example: JMP ($13)
- Zero page, indirect - A single byte version of the above, which may not even exist!
Stay tuned while I sort this one out.
Two sequential bytes in the zero page contain the lsb, msb of a 16 bit address,
which is the address to jump to.
Used only by JMP, Example: JMP ($13)
- Zero page, indexed indirect - can only be used with X.
The contents of X are added to the zero page location given,
then that address is the first of two bytes that give the address to use.
Example: LDA ($13,X) This implies a table of 2 byte addresses in the zero page.
- Zero page, indirect Y - can only be used with Y.
A 16 bit pointer is fetched from the zero page at the address indicated in the
instruction, then the contents of Y are added to this address.
Example: LDA ($24),Y
This implies a single two byte pointer in the zero page to a byte table elsewhere.
The Stack
The stack always and only uses memory from 0100 to 01ff (i.e. the stack lives in page 1).
Notice that this has implications for hardware design - you better put a block of RAM starting
at address zero and big enough to provide for both pages 0 and 1. Notice the implication here
that page zero will be ram and that startup code must initialize all zero page contents that matter.
The usual thing to do is to initialize the stack pointer to 0xff. Once this is done, the first
value pushed will go to 0x1ff and SP will become 0x1fe. The stack pointer points to the empty
location above the top of the stack where the next push will go.
Vector locations
After reset, the processor loads the PC from FFFC (low byte)
and FFFD (high byte) and away she goes.
There are two other vectors (lsb first),
the full set of 3 is:
- FFFA, FFFB - NMIB vector
- FFFC, FFFD - reset vector
- FFFE, FFFF - brk/irqb vector
Feedback? Questions?
Drop me a line!
Tom's Computer Info / tom@mmto.org