May 1, 2025
STM32H743 Nucleo board -- addresses
The TRM (RM0433) is the resource for this.
Section 2.3 on page 128 is the place to start.
We have a 4G address space divided into 8 blocks of 512M.
Our chips has 2M of flash and 1M of sram.
The SRAM is spread around in interesting ways.
Flash in in two banks:
- 0x0800_0000 = bank 1
- 0x0810_0000 = bank 2
SRAM is interesting, as we have special flavors:
- 0x0000_0000 to 0x0000_ffff (64K) - ITCM
- 0x2000_0000 to 0x2001_ffff (128K) - DTCM
- 0x2400_0000 to 0x2407_ffff (512K) - AXI SRAM
- 0x3000_0000 to 0x3001_ffff (128K) - SRAM1
- 0x3002_0000 to 0x3003_ffff (128K) - SRAM2
- 0x3004_0000 to 0x3004_7fff (32K) - SRAM3
- 0x3800_0000 to 0x3800_ffff (64K) - SRAM4
Why all the special ram designations and sections?
The sections in part have to do with power domains (D1, D2, and D3).
TCM is "tightly coupled ram) which is directly connected
to the Cortex-M7 core. ITCM runs at CPU clock speeds without
wait states and is for instructions.
DTCM is for data - it allows (for example) dual 32 bit access
for instruction pairs (superscalar operation).
GPIO and Console UART (uart3)
See page 131 and 134.
- 0x4000_4800 -- usart3
- 0x5802_0000 -- Gpio-A
- 0x5802_0400 -- Gpio-B
- 0x5802_0800 -- Gpio-C
- 0x5802_4400 -- RCC
- 0x4004_0000 -- USB1 OTG HS
- 0x4008_0000 -- USB2 OTG FS
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Tom's Computer Info / tom@mmto.org